In a current sense amplifier circuit disclosed in Japanese unexamined patent application publication No. H11(1999)-149790, as is shown in FIG. 4, stored information is read as a current value from bit lines BL (0) to BL (n) of a semiconductor memory section 100 via column select transistors T8, T9, and a common data line N3 coupled to a current sense amplifier circuit 200.
In the current sense amplifier circuit 200, the current for the data read from the memory on the common data line N3 is supplied to the source of an n-channel transistor T300, amplified by the transistor T300 and a p-channel transistor T400 connected to a power supply, and output via a node 400 to an n-channel transistor T600. The transistor T600 forms an amplification circuit with a p-channel transistor T700 and the amplification circuit converts the data from the memory that was input as the current value to a voltage value and outputs the voltage as an output from the current sense amplifier circuit 200.
Prior to the current-voltage conversion operation, the node 400 and the common data line N3 are precharged and the bit lines connected by the column select transistors are precharged through the common data line N3. The precharge operation is performed by making the p-channel transistor T400 and the p-channel transistor T500 conductive. The transistor T400 is conductive during a complete period of the current-voltage conversion operation and the precharge operation and the transistor T500 mainly carries out the precharge operation for a short period prior to the current-voltage conversion operation.
In a non-volatile semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 2002-237193, a similar sense amplifier is also disclosed. A PMOS transistor is used as the transistor that carries out the precharge operation.
However, in the above background art, the p-channel transistor or PMOS transistor is used as the transistor for precharge and precharges the node in the current sense amplifier circuit while, at the same time, precharging the common data line and the bit lines. As the capacity of non-volatile semiconductor memory devices expands, the wiring length of the common data line increases and a greater number of memory cells are connected to the bit lines. With much more wiring capacitances, the sense amplifier is required to perform high-speed precharge operations in advance of performing high-speed current-voltage conversion operation. The sense amplifier circuit needs to be equipped with the p-channel transistor or PMOS transistor having a sufficient current supply capability and the transistor size must be larger. This poses a problem in that higher integration is required for non-volatile semiconductor memory devices together at the same time as capacity expansion is desired for non-volatile semiconductor memory devices.
A large transistor has large parasitic capacitances induced by a gate oxide layer between its gate and drain and induced by the PN junction between the drain and the substrate and these parasitic capacitances are added to the node in the current sense amplifier circuit. In the current-voltage conversion operation following the completion of the precharge operation, these parasitic capacitances give rise to a problem, as they cause a delay in potential charge at the internal node in response to current for data from the memory, input to the current sense amplifier circuit, which might result in deterioration in the speed or sensitivity of current sensing. Also, through these parasitic capacitances, capacitance coupling may take upon a level transition of a bias voltage to the gate terminal, which might cause a fluctuation of the level of the voltage at the internal node. This poses a problem whereby the level fluctuation of the voltage to which the input current will be converted might cause a conversion error.
Here, in order to avoid the above problems, it is conceivable to configure the sense amplifier circuit with an NMOS transistor of the same size with a high current drivability instead of the PMOS transistor as the transistor for precharge.
However, when the node connected to the drain terminal of the NMOS transistor in which a power-supply voltage is applied to its gate terminal is precharged to a high potential level, it is precharged to the level of the power-supply voltage less a threshold voltage. In view of extensive applications of low power-supply voltage expected in future non-volatile semiconductor memory devices, when the voltage level to be increased by the precharge operation is high, but so limited, it narrows the voltage range in which the circuit operates and this poses a problem in which it might be hard to ensure operating within predetermined margins.
Information stored in a memory cell is read and its state is determined by presence or absence of a current. When the data read from the memory cell corresponds to no current flow, the internal node in the current-voltage conversion circuit remains at the precharged voltage level; when the data corresponds to a current flow, the precharged voltage level is stepped down. Thus, upon the end of the precharge operation, a transition of the gate voltage of the NMOS transistor to a low level takes place to make the transistor non-conductive and, in consequence, it can be supposed that the precharged voltage level falls by capacitance coupling through the parasitic capacitances. Since the voltage level precharged with the NMOS transistor is equal to the power-supply voltage less the threshold voltage, this level will be stepped down to a still lower voltage level, when affected by the capacitance coupling. This poses the following problem. In instances where the sense amplifier circuit is configured such that this voltage is compared with a reference voltage and differential amplification is performed to ensure reading of data from the memory, a data read error might occur.
The present invention has been made to solve at least one problem with the above prior art and aims to provide a current-voltage conversion circuit and its control method that can achieve both enhancing the speed or sensitivity of current sensing and precharging at a higher speed together in compact circuitry, while preventing a conversion error in the process of current-voltage conversion, and that can function well with a low power-supply voltage.